A Systematic Approach Towards the Implementation of a Low-Noise Amplifier in Sub-Micron CMOS Technology

Low-noise amplifiers (LNAs) are critical components for a wide variety of electronic circuits ranging from aerospace to Bluetooth applications. Typically, in the design phase preceding fabrication, an LNA needs to be designed/tuned for a given set of specifications (e.g. noise figure, power consumption, voltage gain etc.), which tend to be application-dependent. Traditional design based on simulation tools and trial-and-error is human-intensive and requires a high-degree of expertise from the circuit designer. As such, computer aided design (CAD) tools for LNA design are in great demand. This paper presents a new and systematic CAD approach for the design and tuning of LNAs in sub-micron CMOS technology. The approach has multiple phases. In the first phase, a detailed pre-analysis of the design specifications is carried out leading to knowledge-based ranking and selection of an appropriate LNA topology. In the design phase, concepts of single-stage design are exploited and the actual circuit is designed in a modular fashion leading to the initial design. Finally, as in any CAD approach, this design is put through a tuning phase so as to meet the given specifications. LNA design examples presented in the paper illustrate the proposed approach. Resulting circuits are shown to exceed the given specifications confirming its usefulness to designers