Title :
An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter
Author :
Jusoh, Nurul Fatihah ; Haron, Muhammad Adib ; Sulaiman, Fuziah
Author_Institution :
Fac. of Electr. Eng., Univ. Teknol. MARA, Shah Alam, Malaysia
Abstract :
To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol. Utilizing the ModelSim-Altera, RTL model of the shift converter was developed and synthesized then stimulated using TimeQuest Timing Analyzer to observe its functionality.
Keywords :
Zigbee; field programmable gate arrays; peripheral interfaces; power convertors; protocols; radio networks; FIFO; FPGA; ModelSim-Altera; RS232 embedded converter; RTL model; TimeQuest timing analyzer; Verilog HDL language; Zigbee protocol; bidirectional shift converter block technique; system communication demands; system wireless communication; universal serial bus converter; Clocks; Engines; Field programmable gate arrays; Hardware design languages; Protocols; Registers; Universal Serial Bus; FIFO; FPGA; Shift Converter; UART; USB;
Conference_Titel :
Control and System Graduate Research Colloquium (ICSGRC), 2012 IEEE
Conference_Location :
Shah Alam, Selangor
Print_ISBN :
978-1-4673-2035-1
DOI :
10.1109/ICSGRC.2012.6287165
