Title :
High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics
Author :
Tanabe, N. ; Kobayashi, S. ; Miwa, T. ; Amamuma, K. ; Mori, H. ; Inoue, Naoko ; Takeuchi, T. ; Saitoh, S. ; Hayashi, Y. ; Yamada, J. ; Koike, H. ; Hada, H. ; Hunio, T.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.
Keywords :
ferroelectric storage; integrated memory circuits; random-access storage; 8 kbit; FeRAM test chip; cell capacitors characteristics; double layer metal process; high tolerance operation; nonvolatile ferroelectric memories; peripheral circuits; read operation; sense amplifiers; Capacitors; Circuit testing; Degradation; Fabrication; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Operational amplifiers; Random access memory; Voltage;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689226
