Abstract :
Notice of Violation of IEEE Publication Principles
"Spur and Noise Reduction Techniques in Ring Oscillator Based Frequency Synthesizers for Broadcast Receiver SoCs"
by Maxim, A.
in the IEEE Radio and Wireless Symposium, January 2008.
After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.
Specifically, the paper contains references to falsified papers. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.This paper presents a multi-regulator ring- oscillator based frequency synthesizer for broadcast satellite TV receiver applications. High reverse-PSRR shunt regulators were used to close locally the noise of the digital blocks and prevent its coupling to the sensitive analog blocks, while high forward-PSRR series regulators reduce the supply injected spurs. A high amplitude XTAL oscillator and a VT biased squaring buffer with input RC filter were used to reduce the digital spur coupling to the crystal bondwire. The loop filter was integrated on-chip by using a noiseless resistor multiplication architecture, while the equivalent VCO gain was reduced using a nois- attenuating resistor divider. The VCO supply pushing was minimized using a low noise dual series regulator, while the digital divider supply current ripple was prevented from getting into the supply bondwire by a series-shunt regulator.PLL performance includes: 0.9-2.2 GHz frequency range, <1deg quadrature outputs phase mismatch, <1.4degrms integrated phase noise, <50dBc coupled spurs and <-60dBc reference spurs, 130mW power and 0.3mm2 die
Keywords :
active filters; frequency synthesizers; interference suppression; system-on-chip; television broadcasting; television receivers; voltage-controlled oscillators; VT biased squaring buffer; broadcast receiver SoC; broadcast satellite TV receiver; crystal bondwire; digital divider; equivalent VCO; frequency synthesizers; high amplitude XTAL oscillator; input RC filter; low noise dual series regulator; noise attenuating resistor divider; noise reduction techniques; noiseless resistor multiplication architecture; ring oscillator; spur reduction; Filters; Frequency synthesizers; Noise reduction; Notice of Violation; Radio broadcasting; Receivers; Regulators; Ring oscillators; Satellite broadcasting; PLL; broadcast tuner; ring oscillator; spur;
