DocumentCode :
3141082
Title :
A Timing Verification System Based on Extracted MOS/VLSI Circuit Parameters
Author :
Ng, Pauline ; Glauert, Wolfram ; Kirk, Robert
Author_Institution :
American Microsystems, Inc., Santa Clara, CA
fYear :
1981
fDate :
29-1 June 1981
Firstpage :
288
Lastpage :
292
Abstract :
The Path Analysis program provides logic and circuit design checking for signal propagation delay constraints. The program is useful for optimizing network performance. Checking and optimization are traditionally performed by manual inspection and incompletely verified by logic and circuit simulation. The Path Analysis program completely verifies signal propagation delays against design constraints. Checks are performed either with user supplied logic simulation data or parameters extracted from the physical IC layout information.
Keywords :
Circuit simulation; Circuit synthesis; Inspection; Logic circuits; Logic design; Propagation delay; Signal analysis; Signal design; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1981. 18th Conference on
Type :
conf
DOI :
10.1109/DAC.1981.1585365
Filename :
1585365
Link To Document :
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