A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs

Author

Kachi, T. ; Shoji, K. ; Yamashita, H. ; Kisu, T. ; Torii, K. ; Kumihashi, T. ; Fujisaki, Y. ; Yokoyama, N.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1998

fDate

9-11 June 1998

Firstpage

126

Lastpage

127

Abstract

A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.

Keywords

annealing; ferroelectric capacitors; ferroelectric storage; random-access storage; 0.5 micron; 4 Kbit; angled-capacitor layout; ferroelectric capacitor; ferroelectric random access memory; oxygen annealing; polysilicon plug; remanent polarization; single-transistor/single-capacitor memory cell; stacked capacitor; Annealing; Capacitors; Degradation; Electrodes; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Plugs; Polarization; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689227

Filename

689227