Title :
Normally-off PLED (Planar Localised Electron Device) for non-volatile memory
Author :
Mizuta, H. ; Nakazato, K. ; Piotrowicz, P.J.A. ; Itoh, K. ; Teshima, T. ; Yamaguchi, K. ; Shimada, T.
Author_Institution :
Hitachi Cambridge Lab., Hitachi Europe Ltd., Cambridge, UK
Abstract :
An advanced Planar Localised Electron Device (PLED) is presented for use as a non-volatile and high-speed random access memory with very low power consumption. A new tunnel barrier configuration is introduced to achieve both write time shorter than 1.0 nsec and retention time over 10 years. An operation scheme based on extremely high ON/OFF current ratios is demonstrated for the first time by conducting numerical simulation of tunnel currents.
Keywords :
high-speed integrated circuits; low-power electronics; random-access storage; tunnelling; ON/OFF current ratio; low power circuit; nonvolatile high-speed random access memory; normally-off PLED; numerical simulation; planar localised electron device; retention time; tunnel barrier; tunnel current; write time; Diodes; Electron devices; Laboratories; Nonvolatile memory; Numerical simulation; Random access memory; Read-write memory; Silicon; Tunneling; Voltage;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689228
