Title :
Verification and Optimization for LSI & PCB Layout
Author :
Brady, H. Nelson ; Smith, Robert J., II
Author_Institution :
V-R Information Systems, Inc., Austin, TX
Abstract :
Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.
Keywords :
Data mining; Data structures; Design optimization; Fabrication; Information systems; Integrated circuit interconnections; Large scale integration; Layout; Optimized production technology; Wiring;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585383
