Holes Effects on RF MEMS Parallel Membranes Capacitors

Parallel membrane RF MEMS capacitors are designed with small diameter holes in the top plate of capacitance due to fabrication process requirements for sacrificial layer removal and modification of dynamic behaviour of the structure. The impact of hole characteristics (size, pitch and ligament efficiency) on the component performance is not very well documented in current literature. Only rules of thumb are used in the design without giving much justification. This study explores and assesses the effect of larger holes with different pitches and ligament efficiencies in fixed top membrane by means of simulations with CoventorWare analyzer simulation software and practical probing tests conducted on specifically designed set of RF MEMS capacitors. The approach used in this study is by varying the RF capacitance with two different axis of comparison. The first being a set of MEMS capacitors having different sized holes of equal combined surface and the second having fixed number of holes with different diameters. The experimental results converge quite adequately with the designed and simulated results giving a clear performance trend and appropriate designer solution. The outcome of this paper improves the degree of freedom of the designer with respect to the manufacturing difficulties for sacrificial layer removal associated to better dynamics and RF performances of the components