Thermoelectric test structures to measure the heat capacity of CMOS layer sandwiches

We report a novel thermal characterization microstructure to measure the heat capacity of CMOS IC layer sandwiches. This parameter is relevant, e.g., for the dynamic response of thermal CMOS microtransducers. The test structures were fabricated using the commercial 2 μm low voltage CMOS process of EM Microelectronic Marin, Switzerland, followed by maskless micromachining. The Seebeck coefficient of gate polysilicon against the lower CMOS metal is used to monitor the propagation of heat waves along the microstructure. At 300 K, volumetric heat capacities of 1.82±0.12×10⁶ Jm^-3 K^-1 and 1.66±0.06×10⁶ Jm^-3 K^-1 were obtained, respectively, for the passivation sandwich and the full sandwich of CMOS dielectrics including the lower metal and polysilicon