Title :
High aspect ratio single crystalline silicon microstructures fabricated with multi layer substrates
Author :
Gui, C. ; Jansen, H. ; de Boer, M. ; Berenschot, J.W. ; Gardeniers, J.G.E. ; Elwenspoek, M.
Author_Institution :
MESA Res. Inst., Twente Univ., Enschede, Netherlands
Abstract :
This paper reports a method for making high aspect ratio single crystalline silicon (SCS) microstructures on multi layer substrates using chemical mechanical polishing (CMP), silicon fusion bonding (SFB) and reactive ion etching (RIE) techniques. First Si-SiO2-PolySi-SiO2-Si sandwich wafers were fabricated using CMP and SFB. Then microstructures were fabricated on these sandwich wafers using an one run self-aligned RIE process, where polysilicon was used as the sacrificial layer. Polishing and bonding of low pressure chemical vapour deposition (LPCVD) polysilicon were studied. A LPCVD Si3+xN4 polishing stop layer technique was developed to accurately control the final thickness of the device layer. The uniformity of the device layer was improved as well
Keywords :
chemical vapour deposition; elemental semiconductors; micromechanical devices; polishing; silicon; silicon compounds; sputter etching; wafer bonding; Si; Si-SiO2-PolySi-SiO2-Si sandwich wafers; Si-SiO2-Si-SiO2-Si; Si3+xN4 polishing stop layer technique; Si3N4-Si; chemical mechanical polishing; high aspect ratio single crystalline silicon microstructures; low pressure chemical vapour deposition polysilicon; multi layer substrates; one run self-aligned RIE process; reactive ion etching; silicon fusion bonding; Annealing; Chemical processes; Chemical vapor deposition; Crystal microstructure; Crystallization; Etching; Oxidation; Silicon; Thickness control; Wafer bonding;
Conference_Titel :
Solid State Sensors and Actuators, 1997. TRANSDUCERS '97 Chicago., 1997 International Conference on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-3829-4
DOI :
10.1109/SENSOR.1997.613731
