Title :
Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs
Author :
Miletic, Igor ; Mason, Ralph
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont.
Abstract :
A 120MHz fractional-N frequency synthesizer was implemented in a standard 0.18mum CMOS process with an on-chip multiphase voltage-controlled oscillator (VCO). The proposed architecture uses multiphase outputs of the VCO to decrease quantization noise from the sigma-delta (SigmaDelta) modulator. Results show 6dB decrease in quantization noise for every two fold increase in the number of phases, which allows increase in loop bandwidth. The VCO phase noise was measured to be -104dBc/Hz at 200kHz offset. The loop bandwidth can be increased to 700kHz and still maintain in-band quantization noise below -100dBc/Hz. The power consumption of the synthesizer is 5.4mW with a 1.8V supply and it occupies an active area of 750mum times 550mum. The intended application is subharmonic injection higher frequency VCO and as a clock generator in a subsampling analog-to-digital converter (ADC)
Keywords :
CMOS integrated circuits; frequency synthesizers; phase locked loops; quantisation (signal); sigma-delta modulation; voltage-controlled oscillators; 0.18 micron; 1.8 V; 120 MHz; 200 kHz; 504 mW; 700 kHz; CMOS process; analog-to-digital converter; bandwidth expansion; clock generator; frequency synthesizer; on-chip multiphase voltage-controlled oscillator; phase locked loops; power consumption; quantization noise; sigma-delta PLL; sigma-delta modulator; Active noise reduction; Bandwidth; CMOS process; Delta-sigma modulation; Frequency synthesizers; Noise measurement; Phase measurement; Phase noise; Quantization; Voltage-controlled oscillators;
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
DOI :
10.1109/CCECE.2006.277635