Title :
Circuit Recognition and Verification Based on Layout Information
Author :
Ablasser ; Jager, U.
Author_Institution :
AEG-Telefunken, Semiconductor Department, Heilbronn, F.R. Germany
Abstract :
The mathematical and technical background information for our highly efficient procedure of circuit recognition and verification from layout information is presented. Complete verification and extremely short computing times are the main goals. This procedure can be performed for bipolar as well as for MOS technologies and is part of the whole layout-control system LOCATE.
Keywords :
Automatic testing; Circuit testing; Circuit topology; Design automation; Information analysis; Information retrieval; Network topology; Performance analysis; Standards publication; System testing;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585427
