NBTI-aware technique for transistor sizing of high-performance CMOS gates

NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of CMOS circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance CMOS gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32 nm technology using our methodology presents 6% delay reduction at year 3 compared to a traditional sizing methodology, both using the same area. For a NAND gate we achieved a delay improvement up to 11%. The methodology here proposed can be extended to other CMOS logic gates, including complex gates.