Title :
Turning JTAG inside out for fast extended test access
Author :
Devadze, Sergei ; Jutman, Artur ; Aleksejev, Igor ; Ubar, Raimund
Author_Institution :
Testonica Lab. OU, Tallinn
Abstract :
This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS.
Keywords :
boundary scan testing; printed circuit testing; printed circuits; boundary scan instructions; electronic manufacturing; fast extended test access; in-system programming; printed circuit boards; system-level testing; test access mechanism; test access protocol; turning JTAG; Access protocols; Circuit testing; Field programmable gate arrays; Flash memory; Hardware; Printed circuits; Pulp manufacturing; Software testing; System testing; Turning;
Conference_Titel :
Test Workshop, 2009. LATW '09. 10th Latin American
Conference_Location :
Buzios, Rio de Janeiro
Print_ISBN :
978-1-4244-4207-2
Electronic_ISBN :
978-1-4244-4206-5
DOI :
10.1109/LATW.2009.4813799