Title :
A High-Level Power Model for MPSoC on FPGA
Author :
Piscitelli, Roberta ; Pimentel, Andy D.
Author_Institution :
Comput. Syst. Archit. Group, Univ. of Amsterdam, Amsterdam, Netherlands
Abstract :
This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, e.g., commonly-used instruction-set simulator (ISS) based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of Micro blaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.
Keywords :
field programmable gate arrays; multiprocessing systems; system-on-chip; FPGA; MPSoC; Micro blaze processors; Virtex-6 FPGA board; abstract execution profiles; event signatures; high-level power model; multiprocessor systems-on-chip architectures; power estimation technique; system-level design space exploration; Clocks; Computational modeling; Estimation; Power demand; Program processors; Table lookup;
Conference_Titel :
Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
978-1-61284-425-1
Electronic_ISBN :
1530-2075
DOI :
10.1109/IPDPS.2011.133