Title :
Low-power GPS receiver design
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
This paper describes the design of a low-power global positioning system (GPS) receiver implemented in CMOS technology. The primary GPS ranging signal is broadcast at a frequency of 1.575 GHz, modulated by a pseudo-noise sequence at a chip rate of 1 MHz. The design of this low-power GPS receiver emphasizes the circuit techniques and architectural trade-offs employed in minimizing the energy needed for each position estimate
Keywords :
CMOS integrated circuits; Global Positioning System; binary sequences; distance measurement; modulation coding; pseudonoise codes; radio receivers; 1.575 GHz; CMOS technology; GPS; global positioning system; low-power receiver; pseudo-noise sequence modulation; ranging signal; Broadcasting; CMOS technology; Circuits; Clocks; Degradation; Delay; Frequency; Global Positioning System; Military satellites; Modulation coding; Phase measurement; Satellite broadcasting; Synchronization;
Conference_Titel :
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4997-0
DOI :
10.1109/SIPS.1998.715763
