A MOS Modelling Technique for 4-State True-Value Hierarchical Logic Simulation or Karnough Knowledge

Modelling strategies and techniques are given for static and dynamic MOS transistors in a 4--state (0/low, 1/high, Z/high-impedance, U/undefined) logic simulator environment. General MOS modelling problems are presented and a set of workable solutions are developed. Experience with these techniques is shown along with examples of NMOS simulation applications. This paper discusses a technique with specific conventions for modelling MOS devices at the "logical transistor" gate level. The technique is not the optimal general solution, but was found to be satisfactory for retrofitting an existing 4--state logic simulator to include MOS capabilities. The technique is not meant to replace analog circuit simulation, but is aimed at increasing the accuracy of MOS logic (gate level) simulations. We begin with a general bus model and extend it to handle transistors, pullups and pulldowns, and dynamic MOS transfer gates. Extensions are shown for a bidirectional transfer gate model that can be connected in any topological configuration.