Title :
An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3
Author :
Tanaka, Chiyoji ; Murai, Shinichi ; Tsuji, Hiroo ; Yahara, Toshihiko ; Okazaki, Kaoru ; Terai, Masayuki ; Katoh, Reiji ; Tachibana, Mikio
Author_Institution :
Computer Laboratory Mitsubishi Electric Corp., Kamakura, Japan
Abstract :
Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.
Keywords :
Computational modeling; Computer simulation; Data engineering; Design automation; Laboratories; Logic arrays; Logic design; Manuals; Routing; Wire;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585450
