Title :
SHARPS: A Hierarchical Layout System for VLSI
Author :
Chiba, Toru ; Okuda, Noboru ; Kambe, Takashi ; Nishioka, I. ; Inufushi, Tsuneo ; Kimura, Seiji
Author_Institution :
SHARP Corporation, Nara, Japan
Abstract :
A hierarchical layout system for VLSI provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. Several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom LSI´s.
Keywords :
Acceleration; Costs; Fabrication; Ferroelectric films; Integrated circuit layout; Large scale integration; Nonvolatile memory; Random access memory; Routing; Very large scale integration;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585451
