Title :
A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic
Author :
Hafer, Louis ; Parker, Alice C.
Author_Institution :
Carnegie-Mellon University
Abstract :
This paper describes a method for formally modelling digital logic using algebraic relations. The types of relations necessary for modelling digital logic at the register-transfer (RT) level are developed. An extension of the model is shown which can be used for logic synthesis at the RT level.
Keywords :
Binary search trees; Boolean algebra; Circuit analysis; Circuit synthesis; Design optimization; Hardware; Linear programming; Logic design; Logic functions; Timing;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585454
