DocumentCode :
3142749
Title :
AREA-Time Efficient Addition in Charge Based Technology
Author :
Montoye, Robert K.
Author_Institution :
University of Illinois at Urbana-Champaign, Urbana, IL
fYear :
1981
fDate :
29-1 June 1981
Firstpage :
862
Lastpage :
872
Abstract :
Using the model developed by Mead and Conway for charge based technology, a methodology for the production of area-time efficient adders which imbeds the buffering required to drive large loads caused by the carry-lookahead tree has been developed. This methodology can be used to produce an 0(logN) time and 0(NlogN) area layout. Additionally, an algorithm was written to produce minimal silicon area layouts for a given time bound. This algorithm involves optimization at both the cellular level and the layout level in an iterative fashion to allow the relevant technological parameters to play a role in the cellular design phase. Results of the algorithm including examples and an area-time curve for a 48 bit adder using typical 5 micron NMOS [MeCo80] are displayed.
Keywords :
Algorithm design and analysis; Computer science; Cost function; Delay; Design optimization; Iterative algorithms; Logic design; MOS devices; Production; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1981. 18th Conference on
Type :
conf
DOI :
10.1109/DAC.1981.1585456
Filename :
1585456
Link To Document :
بازگشت