Notice of Violation of IEEE Publication PrinciplesA single-chip digitally enhanced radio receiver for DBS satellite TV applications

Notice of Violation of IEEE Publication Principles

"A Single-chip Digitally Enhanced Radio Receiver for DBS Satellite TV Applications"
by A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, D. Trager, M. Reid
in the Proceedings of the 2008 IEEE Radio and Wireless Symposium,
Page(s):787-790

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A digital low-IF receiver for satellite TV applications was realized in 110 nm CMOS taking advantage of high speed and moderate resolution ADCs and high digital processing power available in nanometer CMOS. A discrete gain step signal path and a digital power level measurement together with a digital AGC loop implementation resulted in lower receiver area and power and a smaller noise figure penalty. Image rejection in excess of 50 dB was achieved by using a continuous digital I/Q mismatch correction engine that relaxes the matching requirements on the a- alog front-end and thus reduces the occupied die area. A dynamic digital clock frequency management algorithm was implemented to avoid receiver de-sensitization due to digitally coupled in-band spurs. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50 dBc spurs, <0.2 s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3 V supply and 1.8 x 4.8 mm² die area.