A prototype analog/mixed-signal fast fourier transform processor IC for OFDM receivers

Author

Lehne, Mark ; Raman, Sanjay

Author_Institution

Wireless Microsystems Lab., Blacksburg

fYear

2008

fDate

22-24 Jan. 2008

Firstpage

803

Lastpage

806

Abstract

A prototype FFT processor IC that reduces linearity requirements of analog-to-digital converters in broadband orthogonal-frequency-division-multiplexing (OFDM) receivers is presented. The processor is based on a time-interleaving bank of sample-and-holds and a discrete- time analog multiplication based FFT. The circuit design of the prototype IC is presented and measurement results from the 0.13 mum test chip are shown. The FFT length-8 prototype successfully demodulates a complex OFDM signal at 1 GSps while drawing 25 milliwatts of power from a 1.2 Volt supply and achieving an error vector magnitude of 2.8%.

Keywords

OFDM modulation; analogue-digital conversion; fast Fourier transforms; mixed analogue-digital integrated circuits; radio receivers; radiofrequency integrated circuits; FFT processor; IC; OFDM receivers; analog-mixed-signal fast Fourier transform processor; analog-to-digital converters; discrete-time analog multiplication; error vector magnitude; orthogonal-frequency-division-multiplexing receivers; sample-and-holds; size 0.13 mum; time-interleaving bank; Analog integrated circuits; Analog-digital conversion; Circuit synthesis; Circuit testing; Fast Fourier transforms; Integrated circuit testing; Linearity; OFDM; Prototypes; Semiconductor device measurement; Analog multipliers; CMOS analog integrated circuits; Discrete Fourier transforms; Mixed analog-digital integrated circuits; OFDM; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Symposium, 2008 IEEE

Conference_Location

Orlando, FL

Print_ISBN

978-1-4244-1462-8

Electronic_ISBN

978-1-4244-1463-5

Type

conf

DOI

10.1109/RWS.2008.4463614

Filename

4463614