Title :
A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology
Author :
Chang, M.H. ; Ting, J.K. ; Shy, J.S. ; Chen, L. ; Liu, C.W. ; Wu, J.Y. ; Pan, K.H. ; Hou, C.S. ; Tu, C.C. ; Chen, Y.H. ; Sue, S.L. ; Jang, S.M. ; Yang, S.C. ; Tsai, C.S. ; Chen, C.H. ; Tao, H.J. ; Tsai, C.C. ; Hsieh, H.C. ; Wang, Y.Y. ; Chang, R.Y. ; Chen
Author_Institution :
Res. & Dev., Taiwan Semicond. Manuf. Co., Shin-Chu, Taiwan
Abstract :
A multiple-Vt high performance, high density and highly manufacturable 0.25 μm CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts/vias, and fully stacked contact/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for 3.3 V I/O or 13 nm for 5 V I/O) with low defect density, and low Vt (∼0.2 V) or native Vt (∼0 V) devices for low power and mixed-mode applications are all demonstrated in this technology.
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; integrated circuit manufacture; integrated circuit metallisation; integrated circuit reliability; isolation technology; surface treatment; 0.25 micron; 2.5 to 5 V; 5 to 13 nm; W; dual gate oxide process; etchback W plug; high density CMOS; highly manufacturable CMOS process; logic/embedded IC foundry technology; low power applications; mixed-mode applications; multiple threshold voltages; multiple-Vt CMOS process; oxide CMP planarization; shallow trench isolation process; stacked contact/vias; CMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Etching; Foundries; Implants; Isolation technology; Manufacturing processes; Voltage;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689236
