DocumentCode
3143168
Title
An Analytical Method for Compacting Routing Area in Integrated Circuits
Author
Ciesielski, M.J. ; Kinnen, E.
Author_Institution
University of Rochester, Rochester, NY
fYear
1982
fDate
14-16 June 1982
Firstpage
30
Lastpage
37
Abstract
An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed.
Keywords
Channel capacity; Compaction; Computational complexity; Integrated circuit interconnections; Integrated circuit layout; Linear programming; Minimization; Pins; Routing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1982. 19th Conference on
Conference_Location
Las Vegas, NV, USA
ISSN
0146-7123
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1982.1585476
Filename
1585476
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