A hierarchical technique to model parametric device variation in non-linear analogue CMOS architectures

A new statistical technique for hierarchically modelling process variation in analogue circuits is presented. An automatic model generator is used to produce a standard behavioural model, which may be augmented to model the effect of low-level parametric variation extracted from Monte-Carlo analysis. A novel reordering algorithm and a blend of polynomial approximation and table-based spline are used to produce fast compact behavioural models accommodating parametric component variation