Title :
A manufacturable and modular 0.25 /spl mu/m CMOS platform technology
Author :
Tsui, P. ; Chuang, H. ; Bhat, N. ; Travis, E. ; Chheda, S. ; Grant, J. ; Gilbert, P. ; Chen, P. ; Poon, S. ; Kaiser, A. ; Anthony, B. ; White, T. ; West, J. ; Vuong, T. ; Mattay, S. ; Kruth, B. ; Perera, Amitha ; Porter, J. ; Schippers, M. ; Yang, I. ; Mi
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
A modular 0.25 /spl mu/m CMOS core technology suitable for high density and high-performance or low-power applications is presented. The key salient features include: simple 1-mask STI, 40 /spl Aring/ high-performance or low-power CMOS transistor modules, cobalt salicide, a practical 2D Optical Proximity Correction (OPC) technique applied to tight-pitch local interconnect and 6-level tiled metallization backend that include unlanded vias and no-cap Inter-Level Dielectric (ILD). This technology is capable of producing state-of-the-art 380 MHz RISC microprocessors (47 mm/sup 2/) with 9.4 /spl mu/m/sup 2/ 6 T bitcell SRAM. The modularity of the process architecture allows the subsequent expansion of the integration to a wide-range of applications.
Keywords :
CMOS digital integrated circuits; CMOS integrated circuits; VLSI; integrated circuit manufacture; integrated circuit metallisation; 0.25 micron; 2D optical proximity correction technique; 380 MHz; CoSi; RISC microprocessors; SRAM; high density type; low-power applications; manufacturable CMOS platform technology; modular CMOS platform technology; no-cap inter-level dielectric; six-level tiled metallization backend; submicron CMOS platform technology; tight-pitch local interconnect; CMOS technology; Computer aided manufacturing; Computer networks; Dielectrics; Implants; Integrated circuit interconnections; Isolation technology; Metallization; Resists; Transistors;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689237
