A Logic Minimizer for VLSI PLA Design

This paper describes LOGMIN, a new, interactive computer aided logic design tool. LOGMIN automates the increasingly complex problems of VLSI PLA design which has made the specification, manipulation, minimization and generation of PLAs difficult to do by hand. LOGMIN allows the specification of both combinational functions and sequential machines. Combinational functions may be described using a variety of operators, intermediate variables or PLA code. A State Machine Description Language (SMDL) was developed for the specification of sequential machines. This paper describes the background and motivation for LOGMIN, the algorithms used and the grammar for SMDL. Several examples are provided.