• DocumentCode
    3143489
  • Title

    Behavioural modelling of mixed-signal circuits using PWL waveforms

  • Author

    Long, D.I.

  • Author_Institution
    Dept. of Electron., Bournemouth Univ., UK
  • fYear
    1997
  • fDate
    35753
  • Firstpage
    42401
  • Lastpage
    42406
  • Abstract
    The development of mixed signal modelling languages such as VHDL-AMS and Verilog-A allows the behaviour of analogue and mixed signal circuits to be described at a higher level than is possible with conventional circuit-level (e.g. SPICE type) simulators. Mixed-signal simulators for these new languages can process such behavioural models far more efficiently than was previously possible. The non-linear characteristics of many circuits require differential equations to be used in the behavioural descriptions. Unfortunately, the methods used to solve these equations in a mixed-signal simulator are more computationally demanding than those required to evaluate the logic expressions used to describe digital circuits. Consequently, the simulation of analogue and mixed-signal circuits is still far less efficient than the simulation of a pure digital circuit. This paper presents an alternative approach to modelling the behaviour of analogue and mixed-signal circuits based upon piecewise linear (PWL) waveforms. Since the signals processed by these models are linearised, direct methods (i.e. non-iterative) can be used to simulate their behaviour. Several alternative methods are discussed. Examples showing the application of this approach to commonly used circuits are developed and the results compared against corresponding models written for conventional simulators. Finally, suggestions are given for implementing these techniques in a VHDL simulators
  • Keywords
    integrated circuit modelling; PWL waveforms; VHDL-AMS; Verilog-A; behavioural modelling; behavioural models; differential equations; direct methods; logic expressions; mixed-signal circuits; nonlinear characteristics; piecewise linear waveforms;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Mixed-Signal AHDL/VHDL Modelling and Synthesis (Ref. No: 1997/331), IEE Colloquium on
  • Conference_Location
    London
  • Type

    conf

  • DOI
    10.1049/ic:19971117
  • Filename
    660666