Title :
Temporal Placement for Run-Time Reconfiguration
Author :
Nahas, Carlos ; Guevara, Ricardo Villalobos ; Groza, Voicu
Author_Institution :
Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont.
Abstract :
In this paper, we propose the use of an algorithm that can improve the performance of the FPGA placement task for run-time reconfiguration (RTR) computing. Previous literature can be referenced for the sake of presenting related work, as well as to present some algorithms that can be used for the placement of static, compile-time reconfigurable devices. These algorithms can then be examined in order to propose a placement algorithm that can be used in further RTR research
Keywords :
field programmable gate arrays; genetic algorithms; logic design; reconfigurable architectures; FPGA placement task; field programmable gate array; run-time reconfiguration; temporal placement; Application specific integrated circuits; Costs; Field programmable gate arrays; Information technology; Logic design; Reconfigurable architectures; Reconfigurable logic; Resource management; Runtime environment; Timing; Run-Time Reconfiguration; placement algorithm;
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
DOI :
10.1109/CCECE.2006.277750
