Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells

A delay locked loop (DLL) is a feedback control system that equalizes the phase of two delayed copies of the same clock signal. The DLL is useful for compensating for the clock distribution delays that arise in many system configurations. Our motivation for designing an all-digital DLL was to ensure that the clock signal (and hence input vectors) received from off-chip via the pad circuits would be synchronized with the distributed and buffered clock signal at the flip-flops (and hence the synchronous datapath signals) within the core of a 250-MHz CMOS integrated circuit (IC) implemented in 180-nm, six-metal technology. Due to an aggressive design schedule and a limited number of designers, it was decided to synthesize the entire IC, including the DLL, from a VHDL model down to black box standard cells. This necessitated a robust, structural-level DLL design that would operate over a broad frequency range while tolerating a range of gate delays. Multiple fall-back operating modes and test features were included to increase the characterizability of the design. The digital delay line was implemented as a cascade containing 256 inverter pairs. Altogether the DLL occupied 28200 sq.microns, which was only 0.405% of the 6.92 sq.mm core of the IC. The fabricated DLL was verified to operate from 14 MHz up to the 166 MHz maximum frequency of the available tester