DocumentCode
3143863
Title
A Layout Synthesis System for NMOS Gate-Cells
Author
Luhukay, J. ; Kubitz, W.J.
Author_Institution
University of Illinois, Urbana, IL
fYear
1982
fDate
14-16 June 1982
Firstpage
307
Lastpage
314
Abstract
A synthesis system for the automatic layout of NMOS gate cells is described. The cells are based on multigrid cell models and are intended for use as part of a chip synthesis system. An outline of the basic concepts of a CAD procedure for the layout synthesis of such cells is given. The main objective is to generate correct and compact cells with controlled growth in area when subjected to modified speed requirements. Both the layout synthesis procedure itself and algorithms are discussed.
Keywords
Automatic logic units; Control system synthesis; Design automation; Geometry; Integrated circuit layout; Integrated circuit synthesis; Libraries; Logic arrays; MOS devices; Programmable logic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1982. 19th Conference on
Conference_Location
Las Vegas, NV, USA
ISSN
0146-7123
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1982.1585516
Filename
1585516
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