Self-compensating the effect of defect generation in advanced CMOS substrates

Time-dependent degradation of transistor parameters is one of the major reliability concerns in current CMOS technologies. Transistor parameters, e.g. threshold voltage, drain current, etc. change due to the formation of defects at the oxide/Si interface; as well as due to charge trapping into defects present within the bulk of the dielectric (e.g., electron trapping for NMOS and hole trapping for PMOS). Device designers often feel that process modifications cannot adequately address such reliability problems without adversely affecting performance metrics. Thus the traditional option has been to operate transistors with an extra guard band voltage, so that regardless of the magnitude of variability or time-dependent parametric shifts, the transistors drivability or drain current remains above certain minimum value. In this paper, we discuss the possibility of self-compensation of parametric degradation (and associated threshold voltage shift) due to interface and oxide defects that might occur at advanced substrates such as strained-Si or III-V materials. We illustrate how these substrate technologies - currently only being studied for performance improvement - can also be engineered to compensate for defect-related threshold voltage shift, with the possibility of reducing the guard-band voltage. Moreover, we demonstrate the viability of the proposed concept of self-compensation using advanced substrates both at the device level, as well as in the circuit level.