Vt instability in high bit-count-per-cell Floating-Gate Non-Volatile memories

Floating gate cell array reliability associated with high-bit-count per cell (multi-level cell with >=3 bit/cell) is investigated. A high operating voltage during P/E operation can cause excessive charge injection into the inter-poly-dielectrics layers (IPD), and subsequent charge displacement will cause data retention or read-disturb problems. The Vt shift due to this charge displacement is related to the cell Vt, the amount of trapped charges the nitride layer and the applied external voltage. For a reliable product operation, the high voltage should be limited to keep the charge in the nitride layer to an acceptable level.