Title :
Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times
Author :
Chowdhury, Shouvik ; Grewal, Gary William ; Banerji, Dilip K.
Abstract :
The rectilinear Steiner tree problem (RSTP) is a classical problem having numerous real-world applications, including VLSI routing. Since the RSTP is NP-hard, developing polynomial heuristics which can produce near optimal solutions has been the primary approach to solve the RSTP. Many of these algorithms (e.g., 1-Steiner) use Hanan points. However, although the algorithms iterate through the entire set of Hanan points, frequently less than 5% of Hanan points appear in the final tree. In this paper, we propose several strategies to reduce the size of the set of Hanan points any iterative algorithm needs to consider, by eliminating points which are less likely to be included in the solution. This results in an improvement in run time, as the iterative algorithm must consider fewer Hanan points. Using our methods, we were able to generate Steiner trees with similar cost to those found when all Hanan points were considered, but with execution time reductions of more than 30%
Keywords :
VLSI; integrated circuit interconnections; iterative methods; network routing; trees (mathematics); Hanan points; Steiner trees; VLSI interconnect routing times reduction; iterative algorithm; very large scale integration; Clustering algorithms; Costs; Iterative algorithms; Joining processes; Polynomials; Quality assurance; Routing; Silicon; Tree graphs; Very large scale integration; Clustering; Rectilinear Steiner tree; VLSI Routing;
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
DOI :
10.1109/CCECE.2006.277830