Title :
Proceedings International Verilog HDL Conference and VHDL International Users Forum
Abstract :
The following topics were dealt with: Verilog HDL and VHDL; compiler technology; language issues; silicon centric RTL; system level design; simulation environment customization; legacy and reuse; verification strategies; validation strategies; testbench strategies; timing; and tools
Keywords :
formal verification; hardware description languages; program compilers; software reusability; timing; virtual machines; VHDL; Verilog HDL; compiler technology; language issues; legacy; reuse; silicon centric RTL; simulation environment customization; system level design; testbench strategies; timing; tools; validation strategies; verification strategies;
Conference_Titel :
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-8415-1
DOI :
10.1109/IVC.1998.660671
