Implication Algorithms for MOS Switch Level Functional Macromodeling, Implication and Testing

In this paper we introduce the concept of implication for MOS switch level circuits. The implication performed on these circuits is an extension of the classical implication now applied to Boolean logic networks. Given the ability to perform implication on MOS circuits we can then; generate functional macromodels of MOS circuits, use these macromodels to verify the Boolean function realized by the MOS circuit extracted from the mask set, generate, directly from the MOS circuit, sets of tests for nodes stuck-at-1 and stuck-at-0 as well as transistors stuck open and stuck short. We present the conceptual framework and algorithms for performing implication on MOS networks. We present examples of MOS implication and discuss extensions of the algorithm to test generation, and to a first order instead of zero order MOS network.