An accurate model for power DMOSFETs including interelectrode capacitances

A novel methodology for modeling power MOS devices using a SPICE-compatible subcircuit is proposed. The interelectrode capacitances are modeled accurately as nonlinear functions of the applied biases. Simulations and measured data support the accuracy of the new models. Various second-order effects relating to the gate capacitance model are discussed, and stratagies are presented to include them in the model. The model parameters can be obtained from device measurements. The approach is verified by gate charge measurements over a wide range of applied biases.<>