Title :
Hierarchical Top-Down Layout Design Method for VLSI Chip
Author :
Adachi, Tohru ; Kitazawa, Hitoshi ; Nagatani, Mitsuyoshi ; Sudo, Tsuneta
Author_Institution :
Musashino Electrical Communication Lab., Nippon Tel. Tel. Public Corp., Musashino, Japan
Abstract :
A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.
Keywords :
Channel capacity; Clocks; Design automation; Design methodology; Programmable logic arrays; Read only memory; Routing; Very large scale integration; Wiring;
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1982.1585585
