• DocumentCode
    3145230
  • Title

    Hierarchical Top-Down Layout Design Method for VLSI Chip

  • Author

    Adachi, Tohru ; Kitazawa, Hitoshi ; Nagatani, Mitsuyoshi ; Sudo, Tsuneta

  • Author_Institution
    Musashino Electrical Communication Lab., Nippon Tel. Tel. Public Corp., Musashino, Japan
  • fYear
    1982
  • fDate
    14-16 June 1982
  • Firstpage
    785
  • Lastpage
    791
  • Abstract
    A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.
  • Keywords
    Channel capacity; Clocks; Design automation; Design methodology; Programmable logic arrays; Read only memory; Routing; Very large scale integration; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1982. 19th Conference on
  • Conference_Location
    Las Vegas, NV, USA
  • ISSN
    0146-7123
  • Print_ISBN
    0-89791-020-6
  • Type

    conf

  • DOI
    10.1109/DAC.1982.1585585
  • Filename
    1585585
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3145230