A systolic architecture for LZ based decompression

Summary form only given. A parallel architecture is proposed for decompression of data compressed using the Lempel-Ziv technique. This paper reports ongoing work towards realizing high speed VLSI hardware for the decompression process. The semi-systolic architecture aims at reducing the interconnect area and global communication, thereby increasing the clock speed. The algorithm has been mapped onto a special purpose VLSI architecture, which requires three global control signals. The hardware can yield a decompression rate of one symbol per clock cycle. The clock speed is improved by minimizing propagation delays