DocumentCode :
3145382
Title :
Top Down Design and Testability of VLSI Circuits
Author :
Basset, Ph. ; Saucier, G.
Author_Institution :
Laboratory IMAG, GRENOBLE, FRANCE
fYear :
1982
fDate :
14-16 June 1982
Firstpage :
851
Lastpage :
857
Abstract :
A top down design methodology of VLSI Circuits used at the University of Grenoble is briefly presented. The choice of a data path is analyzed with respect to testability and diagnosability requirements. Design modifications (in terms of special test control) help achieves the testability requirements. Such an approachm helps to avoid costly techniques like additional scan pathes (LSSD, Bilbo) Combined with dynamic analysis techniques (Stroboscopic analysis), this approach produces efficient VLSI tests.
Keywords :
Circuit synthesis; Circuit testing; Computer errors; Data analysis; Debugging; Design methodology; Laboratories; Logic design; Manufacturing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
ISSN :
0146-7123
Print_ISBN :
0-89791-020-6
Type :
conf
DOI :
10.1109/DAC.1982.1585593
Filename :
1585593
Link To Document :
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