Title :
The design and analysis of a pipeline stage for use in a multistage analog-to-digital conversion
Author :
Deliyannides, G. ; Kwok, H.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
An architecture is proposed to achieve high speed analog-to-digital conversion. This architecture is based on the multi-stage analog-to-digital conversion technique. The multistage method utilizes pipelining to allow concurrent operation of smaller conversion segments. These segments are appended to form a composite result. Through pipelining, a reduction in circuit area is also achieved
Keywords :
analogue-digital conversion; parallel architectures; pipeline processing; architecture; circuit area reduction; concurrent conversion segment operation; high speed analog-to-digital conversion; multistage analog-to-digital conversion; pipeline stage analysis; pipeline stage design; pipelining; Analog-digital conversion; Capacitors; Circuit simulation; Displays; Error correction; Master-slave; Pipeline processing; Rails; Signal resolution; Voltage;
Conference_Titel :
Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on
Conference_Location :
St. Johns, Nfld.
Print_ISBN :
0-7803-3716-6
DOI :
10.1109/CCECE.1997.614811
