DocumentCode
3145613
Title
A procedural language interface for VHDL and its typical applications
Author
Martinolle, Francoise ; Sherer, Adam
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
fYear
1998
fDate
16-19 Mar 1998
Firstpage
32
Lastpage
38
Abstract
Recognizing the utility of a procedural language interface to access VHDL data and interact with a VHDL tool, Cadence has developed a procedural interface which is highly compatible with the Verilog procedural interface. This paper describes the various kinds of applications that can be built using such an interface and shows the interoperability of the Verilog and VHDL procedural interfaces in a mixed language design
Keywords
application program interfaces; digital simulation; hardware description languages; high level synthesis; object-oriented methods; Cadence; VHDL procedural interface; Verilog procedural interface; data access; hardware description language; interoperability; mixed language design; object oriented information model; procedural language interface; simulation; Calculators; Hardware design languages; Logic; Object oriented modeling; Packaging; Propagation delay; Standardization;
fLanguage
English
Publisher
ieee
Conference_Titel
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location
Santa Clara, CA
ISSN
1085-9403
Print_ISBN
0-8186-8415-1
Type
conf
DOI
10.1109/IVC.1998.660677
Filename
660677
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