A selective-input non-binary LDPC decoder architecture

This paper presents a layered selective-input Min-Max decoding algorithm and the associated architecture for non-binary LDPC codes. Compared to the selective-input non-binary decoders presented in the literature, our proposed selective-input implementation can be quite easily realized in order to achieve a higher parallelism and a higher throughput. Also, by using a compensation technique, the error performance of the proposed selective-input implementation is quite close to the original Min-Max algorithm even though a small number of selective inputs is used. Using a 90-nm CMOS process, we implemented a 32-ary (837, 726) decoder that can achieve a throughput of 29.0 Mb/s.