DocumentCode :
3145661
Title :
Memory efficient decoder design of nonbinary LDPC codes
Author :
He, Kai ; Sha, Jin ; Wang, Zhongfeng
Author_Institution :
Sch. of Electron. Sci. & Eng., Nanjing Univ., Nanjing, China
fYear :
2011
fDate :
17-18 Nov. 2011
Firstpage :
44
Lastpage :
47
Abstract :
This paper presents a memory efficient decoding algorithm for the non-binary low-density parity-check (NB-LDPC) codes. Compared to other recently developed Min-Max decoding algorithm, the message memory as well as the average number of iterations has been reduced using the proposed decoding method. Meanwhile, the corresponding decoder architecture is also proposed.
Keywords :
iterative decoding; parity check codes; iterations; low density parity check codes; memory efficient decoder design; message memory; nonbinary LDPC codes; Min-Max; NB-LDPC codes; column-layer; decoder architecture; decoding algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2011 International
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-0709-4
Electronic_ISBN :
978-1-4577-0710-0
Type :
conf
DOI :
10.1109/ISOCC.2011.6138642
Filename :
6138642
Link To Document :
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