A range-scaled 13b 100MS/s 0.13μm CMOS SHA-free ADC based on a single reference

This work describes a 13b 100MS/s 0.13μm CMOS four-step pipeline ADC. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits properly to handle input signals twice as wide as a single on-chip reference range in the first pipeline stage. The range scaling makes reference driving buffers keep a sufficient dynamic voltage headroom and doubles the offset tolerance of a latched comparator without a pre-amp in the flash ADC1. The prototype ADC demonstrates the measured DNL and INL within 0.57LSB and 0.99LSB, respectively. The ADC shows a maximum SNDR of 64.6dB and a SFDR of 74.0dB at 100MS/s, respectively. The ADC with an active die area of 1.2mm² consumes 145.6mW including the high-speed reference buffers and 91mW excluding the buffers at 100MS/s and a 1.3V supply voltage.