DocumentCode :
3145760
Title :
A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique
Author :
Kanemoto, Daisuke ; Ido, Toru ; Taniguchi, Kenji
Author_Institution :
Div. of Electr., Electron. & Inf. Eng., Osaka Univ., Suita, Japan
fYear :
2011
fDate :
17-18 Nov. 2011
Firstpage :
66
Lastpage :
69
Abstract :
A low power and high performance third order delta-sigma modulator for audio applications, fabricated in a 0.18/im CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1dB signal-to-noise ratio (A-weighted) and 101.5dB dynamic range (A-weighted) with 7.5mW power consumption from a 3.3 V supply.
Keywords :
CMOS analogue integrated circuits; delta-sigma modulation; integrated circuit noise; low-power electronics; operational amplifiers; CMOS process; SNR; load capacitance; low-power high-performance third order audio delta-sigma modulator; noise figure 101 dB; noise figure 101.1 dB; noise figure 101.5 dB; opamp sharing technique; optimal operation timing; power 7.5 mW; power consumption; signal-to-noise ratio; size 0.18 mum; third order noise shaping; voltage 3.3 V;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2011 International
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-0709-4
Electronic_ISBN :
978-1-4577-0710-0
Type :
conf
DOI :
10.1109/ISOCC.2011.6138647
Filename :
6138647
Link To Document :
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