A 6 bit linear binary RF DAC in 0.25µm SiGe BiCMOS for communication systems

This paper presents a circuit technique to improve the frequency domain behavior of the binary weighted digital to analog convertors (DAC). It is shown that by adding a current buffer stage, the effect of one of the major drawbacks in this architecture, the impedance variation in every stage, is reduced. To verify the method, a fully binary 6 bit 20.5 Gsps DAC with 1 W power dissipation and measured SFDR higher than 28.2 dBc up to 6.2 GHz input bandwidth was fabricated. The DAC produces 1 Vpp differential output, and less than 60 ps full scale rise time.