A fine-grained timing driven synthesis of arithmetic circuits

Synthesizing a fast arithmetic circuit in high-speed systems is one of the most important design considerations. In particular, it is widely recognized that generating a parallel bit-level structure using full-adder (FA) cells as the design primitive is the most fine-grained and effective method of synthesizing fast arithmetic circuits in RTL synthesis. This work overcomes two inherent limitations of the previous methods of the fast FA-tree construction. Those are (1) the unawareness of slew rate at the input ports of FAs, and (2) the unawareness of load capacitance at the output ports of FAs, which are critically important for achieving a high accuracy of circuit timing estimation. Precisely, we show in this paper that considering the (possibly non-uniform) slew rate and load capacitance at the FA ports in estimating timing in the course of FA-tree construction greatly affects the latency of the resultant arithmetic circuit, and propose a slew rate and load-aware comprehensive FA-tree generation algorithm. We confirm the effectiveness of the proposed algorithm integrating a fine-grained FA timing model through experiments with diverse arithmetic designs commonly appeared in DSP and Multimedia applications. In summary, compared to the designs produced by the best ever known FA-tree synthesis method, our proposed synthesis algorithm is able to reduce the timing on average by 12% further.